求助:modelsim仿真输出波形乱码(附完整VHDL代码及仿真图)

我的程序为使用VHDL语言描述锯齿波,方波,三角波,方波,正弦波等各个模块,然后使用元件例化在顶层文件连接起来,通过选择器选择输出其中一个波形。
单独对每个模块的波形进行调试的时候,波形输出正常。元件例化后使用了quartus17+modelsim10进行联合仿真,仿真波形图却是乱码。又使用quartus91+自带仿真器仿真的时候,输出值正常。

quartus91的仿真输出和modelsim10的仿真波形

  • quartus91仿真波形

    123.png

  • modelsim的仿真波形

程序功能介绍

通过sel端口选择输出的波形,sel=000时输出ZENG模块的锯齿波;sel=001时输出JIAN模块的锯齿波;sel=010时输出DELTA的三角波模块等等。
QQ截图20220427093853.png
QQ截图20220427092917.png

代码

顶层实体

LIBRARY IEEE;
use IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

entity fun_genertor is
    port(
        sel:in std_logic_vector (2 downto 0);
        clk,reset:in std_logic;
        q:out std_logic_vector (7 downto 0)
    );
end;

architecture behave of fun_genertor is

    component ZENG is
        port (
            clk,reset : in  std_logic;
            q: out std_logic_vector(7 downto 0)
        );
    end component ZENG;

    component JIAN is
        port (
            clk,reset : in  std_logic ;
            q: out std_logic_vector(7 downto 0)
        );
    end component JIAN;

    component DELTA is
        port (
            clk,reset : in  std_logic ;
            q: out std_logic_vector(7 downto 0)
            );
    end component DELTA;

    component LADDER is
        port (
            clk,reset: in  std_logic ;
            q: out std_logic_vector(7 downto 0)
        );
    end component LADDER;

    component SINE is
        port (
            clk,clr: in  std_logic ;
            --q: out integer range 0 to 255
            q: out std_logic_vector (7 downto 0)
        );
    end component SINE;

    component SQUARE is
     port (
            clk,clr: in  std_logic ;
            --q: out integer range 0 to 255
            q:out std_logic_vector(7 downto 0)
        );
    end component SQUARE;

    component CH41A is
        port ( 
            sel: in  std_logic_vector(2  downto  0);
            d0,d1,d2,d3,d4,d5: in  std_logic_vector(7 downto  0);
            q: out  std_logic_vector( 7 downto  0)
        );
    end component CH41A;

    signal q_zeng,q_jian,q_delta,q_ladder,q_sin,q_square,q_out:std_logic_vector(7 downto 0);
begin
    U1:ZENG port map(clk=>clk,reset=>reset,q=>q_zeng);
    U2:JIAN port map(clk=>clk,reset=>reset,q=>q_jian);
    U3:DELTA port map(clk=>clk,reset=>reset,q=>q_delta);
    U4:LADDER port map(clk=>clk,reset=>reset,q=>q_ladder);
    U5:SINE port map(clk=>clk,clr=>reset,q=>q_sin);
    U6:SQUARE port map(clk=>clk,clr=>reset,q=>q_square);
    U7:CH41A port map(sel=>sel,d0=>q_zeng,d1=>q_jian,d2=>q_delta,d3=>q_ladder,d4=>q_sin,d5=>q_square,q=>q_out);
    q<=q_out;
end;

testbench文件

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY fun_genertor_vhd_tst IS
END fun_genertor_vhd_tst;
ARCHITECTURE fun_genertor_arch OF fun_genertor_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL clk : STD_LOGIC;
SIGNAL q : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
SIGNAL sel : STD_LOGIC_VECTOR(2 DOWNTO 0);
COMPONENT fun_genertor
    PORT (
    clk : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    reset : IN STD_LOGIC;
    sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    i1 : fun_genertor
    PORT MAP (
-- list connections between master ports and signals
    clk => clk,
    q => q,
    reset => reset,
    sel => sel
    );
init : PROCESS                                               
-- variable declarations                                     
BEGIN     
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS 
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
    -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;
--------------------------------------------------------
--以下代码为自己写的输入信号
--------------------------------------------------------
--时钟信号
Setclk:process
begin
clk<='1';
wait for 10 ns;
clk<='0';
wait for 10 ns;
end process;
--复位信号    
clr_gen:process  
begin   
    reset<='0';  
    wait for 30 ns;  
    reset<='1'; 
    wait;
end process;
--选择信号
setsel:process
begin        
    sel<="000";
    wait for 1000 ns;
    sel<="001";
    wait for 1000 ns;
    sel<="010";
    wait for 1000 ns;
    sel<="011";
    wait for 1000 ns;
    sel<="100";
    wait for 1000 ns;
    sel<="101";
    wait for 1000 ns;
 end process;  

END fun_genertor_arch;

CH41选择模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;

entity CH41A is
     port ( sel: in  std_logic_vector(2  downto  0);
            d0,d1,d2,d3,d4,d5: in  std_logic_vector(7  downto  0);
            q: out  std_logic_vector( 7 downto  0)
                );
end  CH41A;

architecture  CH41_arc of  CH41A is 
begin
    process(sel)
        begin
            case sel is
                when"000"=>q<=d0;  
                when"001"=>q<=d1;  
                when"010"=>q<=d2; 
                when"011"=>q<=d3;  
                when"100"=>q<=d4;  
                when"101"=>q<=d5;  
                when others=>null;
            end case;
    end process;
end CH41_arc;

SIN 正弦波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity  SINE is
      port (clk,clr: in  std_logic ;
        q: out std_logic_vector (7 downto 0)
          );
end  SINE;

architecture SIN_arc of SINE is 
begin 

process(clk,clr)
variable tmp: integer range 0 to  63;
begin    
if clr='0' then
     q<="00000000";
     elsif clk'event and clk = '1'  then
if  tmp=63  then
 tmp:=0;
else
 tmp:=tmp+1;
end if;
case tmp is
when 00=>q<="11111111";  when 01=>q<="11111100";  when 02=>q<="11111110";
when 03=>q<="11111001";  when 04=>q<="11110101";  when 05=>q<="11101111";
when 06=>q<="11101001";  when 07=>q<="11100001";  when 08=>q<="11011001";
when 09=>q<="11001111";  when 10=>q<="11000101";  when 11=>q<="10111010";
when 12=>q<="10101110";  when 13=>q<="10100010";  when 14=>q<="10010110";
when 15=>q<="10001001";  when 16=>q<="01111100";  when 17=>q<="01110000"; 
when 18=>q<="01100011";   when 19=>q<="01010111";   when 20=>q<="01001011";
when 21=>q<="01000000";   when 22=>q<="00110101";   when 23=>q<="00101011";
when 45=>q<="01100011";   when 46=>q<="01110000";   when 47=>q<="01111100";
when 24=>q<="00100010";   when 25=>q<="00011010";   when 26=>q<="00010011";
when 27=>q<="00001101";   when 28=>q<="00001000";   when 29=>q<="00000100";
when 30=>q<="00000001";   when 31=>q<="00000000";   when 32=>q<="00000000"; 
when 33=>q<="00000001";   when 34=>q<="00000100";   when 35=>q<="00001000";
when 36=>q<="00001101";   when 37=>q<="00010011";   when 38=>q<="00011010";
when 39=>q<="00100010";   when 40=>q<="00101011";   when 41=>q<="00110101";
when 42=>q<="01000000";   when 43=>q<="01001011";   when 44=>q<="01010111"; 
when 48=>q<="10001001";  when 49=>q<="10010110";  when 50=>q<="10100010";
when 51=>q<="10101110";  when 52=>q<="10111010";  when 53=>q<="11000101";
when 54=>q<="11001111";  when 55=>q<="11011001";  when 56=>q<="11100001";
when 57=>q<="11101001";  when 58=>q<="11101111";  when 59=>q<="11110101";
when 60=>q<="11111001";  when 61=>q<="11111110";  when 62=>q<="11111100";
when 63=>q<="11111111";   when others=>null;
end case;
end if;
end process;
end SIN_arc;

ZENG 锯齿波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;

entity ZENG is
  port (clk,reset : in  std_logic ;
        q: out std_logic_vector(7 downto 0)
        );
end ZENG;

architecture zeng_arc of zeng is
begin
    process(clk,reset)
        variable tmp: std_logic_vector(7 downto 0);  
    begin    
        if reset='0' then
            tmp:= "00000000";
        elsif clk'event and clk = '1'  then 
            if  tmp="11111111" then
                tmp:= "00000000";
            else
                tmp:=tmp+1;
            end if;
        end if;
        q<=tmp;
    end process;
end zeng_arc;

SQUARE方波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity SQUARE is
   port (clk,clr: in  std_logic ;
        q: out std_logic_vector (7 downto 0)
          );
end  SQUARE;
architecture  SQUARE_arc of  SQUARE is 
signal a:bit; 
begin
process(clk,clr)
variable cnt: integer  range 0  to  63;
begin    
if clr='0' then
  a<='0';
elsif clk'event and clk = '1'  then
if  cnt<63  then
     cnt:=cnt+1; 
else
cnt:=0;
a<=not a;
end if;
end if;
  end process ; 
process(clk,a)
begin    
  if clk'event and clk = '1'  then
if  a='1'  then
q<="11111111";
else
q<="00000000";
end if;
end if;
  end process ;
end SQUARE_arc;

DELTA三角波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity DELTA is
      port (clk,reset : in  std_logic ;
            q: out std_logic_vector(7 downto 0));
end DELTA;
architecture DELTA_arc of DELTA is 
begin
process(clk,reset)
variable tmp: std_logic_vector(7 downto 0);
variable a: std_logic; 
begin    
if reset='0' then
       tmp:= "00000000";
     elsif clk'event and clk = '1'  then 
       if a='0'then
         if  tmp="11111110" then
           tmp:= "11111111";
           a:='1';
        else
           tmp:=tmp+1;
        end if ; 
else
         if tmp="00000001"then
           tmp:="00000000";
           a:='0';
          else
          tmp:=tmp-1;
end if ;
end if ;
end if ;
q<=tmp;
    end process ;
end DELTA_arc;

JIAN锯齿波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;

entity JIAN is
   port (
         clk,reset : in  std_logic ;
q: out std_logic_vector(7 downto 0));
end JIAN;

architecture JIAN_arc of JIAN is 
begin
process(clk,reset) 
variable tmp: std_logic_vector(7 downto 0);
begin    
if reset='0' then
         tmp:= "11111111";
      elsif clk'event and clk = '1'  then 
         if  tmp="00000000" then
            tmp:= "11111111";
         else
         tmp:=tmp-1;
       end if ;
end if ;
q<=tmp;
    end process ;
end  JIAN_arc;

LADDER阶梯波模块

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity  LADDER is
      port (clk,reset: in  std_logic ;
            q: out std_logic_vector(7 downto 0));
end  LADDER;

architecture LADDER_arc of LADDER is 
begin
process(clk,reset) 
variable tmp: std_logic_vector(7 downto 0);
variable a:std_logic;
begin    
if reset='0' then
    tmp:= "00000000";
elsif clk'event and clk = '1'  then 
            if a='0'then
              if  tmp="11111111" then
                  tmp:= "00000000";
                 a:='1';
              else 
 tmp:=tmp+16;
              a:='1';
             end if ;
           else
         a:='0';
       end if ;
end if ;
q<=tmp;
   end process ;
end  LADDER_arc;

单独模块的仿真波形

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