xilinx 7系列FPGA 回读配置文件

Xilinx® 7 series devices allow users to read configuration memory through the SelectMAP, ICAPE2, and JTAG interfaces. There are two styles of readback: Readback Verify andReadback Capture. During Readback Verify, the user reads all configuration memory cells,including the current values on all user memory elements (LUT RAM, SRL, and blockRAM). Readback Capture is a superset of Readback Verify—in addition to reading all configuration memory cells, the current state of all internal CLB and IOB registers is read,and is useful for design debugging.


There are two mandatory bitstream settings for readback: the security setting must not prohibit readback (security:none), and bitstream encryption must not be used.A basic form of security is to prevent readback. The bitstream Security setting can be set to Level1 (disables readback), or Level2 (disables both readback and reconfiguration).

After configuration with an encrypted bitstream,it is not possible to read the configuration memory through JTAG or SelectMAP readback,regardless of the bitstream security setting.


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