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最近在做一个基于FPGA的PPM调制系统,综合没问题烧录后没有波形

求教各位大佬,最近在做一个基于FPGA的PPM调制系统,根据网上找到的代码编写了一段Verilog程序 其中输入的待调制信号是自己编写的用状态机生成的一段二维序列,综合没有问题,烧录到板子上后 外接示波器,示波器上显示不出波形,不知是哪方面出了问题。代码如下:

`timescale 1us/1us
module PPMtz(clk_in,rst_n,data_in,ppmdata,FPGA_TEST2);
input clk_in;
input rst_n;
output ppmdata;
output data_in;
output FPGA_TEST2;
reg [1:0] count;
reg [1:0] xreg;
reg [1:0] yreg;
reg data_in;
reg ppmdata;
reg q;
reg [2:0] pre_state,next_state;
wire clk_out;
clk_out clk_out_inst (
 .inclk0 ( clk_in ),
 .c0 ( clk_out )
 );
parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101;
always @(posedge clk_out or negedge rst_n)  
        begin  
            if(!rst_n)  
                pre_state <= s0;  
            else  
                pre_state <= next_state;  
        end  

    always @(pre_state)  
        begin  
            case(pre_state)  
                s0:  
                    begin  
                        data_in = 1'b0;  
                        next_state <= s1;  
                    end  
                s1:  
                    begin  
                        data_in = 1'b0;  
                        next_state = s2;  
                    end  
                s2:  
                    begin  
                        data_in = 1'b1;  
                        next_state = s3;  
                    end  
                s3:  
                    begin  
                        data_in = 1'b0;  
                        next_state = s4;  
                    end  
                s4:  
                    begin  
                        data_in = 1'b1;  
                        next_state = s5;  
                    end  
                s5:  
                    begin  
                    data_in = 1'b1;  
                    next_state = s0;  
                    end  
                default: next_state = s0;  
            endcase   
        end  

always@(posedge clk_out or negedge rst_n)
if(!rst_n)
begin
count<=2'b11;
q<=0;
yreg<=0;
ppmdata<=1;
end
else
begin
if(count==2'b11)
begin
yreg<=xreg;
q<=~q;
count<=count+1;
end
else
begin
q<=~q;
count<=count+1;
end
if(yreg[0]==1'b0 && count==yreg)
begin
ppmdata<=q;
end
else if(yreg[0]==1'b1 && count==yreg)
begin
ppmdata<=~q;
end
else
ppmdata<=0;
end
always@(posedge clk_out or negedge rst_n)
if(!rst_n)
xreg<=2'b00;
else
if(count[0]==1'b1)
xreg<={xreg[0],data_in};
else
xreg<=xreg;
assign FPGA_TEST2 = clk_out;
endmodule

其中 FPGA_TEST2是我板子上的FPGA的测试引脚,我用来观看我的分频时钟了

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按设计原则来,先仿真。如果要偷懒,直接上内部逻辑分析仪就好了。

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