针对Stratix V ES器件的设计可能无法在TimeQuest中进行定时

此问题会影响DDR2和DDR3,QDR II和RLDRAM II产品。

针对Stratix V ES器件的UniPHY设计可能会在TimeQuest时序分析器中失败保持时序。

解决/修复方法

可能发生两类潜在的故障。如果您发现以下问题之一,则可以忽略违规并尝试在硬件中运行设计:

失败等级1:使用基于Nios II的定序器在UniPHY变体中可能会发生从双区域时钟域到全局时钟域的传输。在以下转移中可能会观察到大约100ps或更少的保持或移除违规:

- from clock "if0|_if0_p0_pll_avl_clock" to clock "if0|_if0_p0_afi_clk" - from clock "if0|_if0_p0_pll_config_clock" to clock "if0|_if0_p0_afi_clk" - from clock "if0|_if0_p0_pll_avl_clock" to clock "if0|_if0_p0_pll_config_clock"

失败等级2:违规可能与核心到外围或外围到核心的转移有关。以下段落说明了不同协议的示例。

DDR2全速率

在以下转移中可能会发现违反约100ps或更少的违规行为:

- from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_write_clk" - from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_dq_write_clk"

DDR3四分之一速率

在以下转移中可能会发现违反约100ps或更少的违规行为:

- from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_write_clk” - from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_p2c_read_clock” - from clock "if0|_if0_p0_pll_hr_clk" to clock "if0|_if0_p0_c2p_write_clock" - from clock "if0|_if0_p0_pll_hr_clk" to clock "if0|_if0_p0_p2c_read_clock" - from clock "if0|_if0_p0_c2p_write_clock" to clock "if0|_if0_p0_write_clk” - from clock "if0|_if0_p0_p2c_read_clock" to clock "if0|_if0_p0_pll_afi_clk" - from clock "if0|_if0_p0_p2c_read_clock" to clock "if0|_if0_p0_write_clk"

QDR II全速率

在以下转移中可能会发现违反约100ps或更少的违规行为:

- from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_leveling_clock_d_*" - from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_leveling_clock_k_*" - from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_leveling_clock_ac_*"

RLDRAM II全速率

在以下转移中可能会发现违反约200ps或更少的违规行为:

- from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_leveling_clock_dq_*" - from clock "if0|_if0_p0_pll_afi_clk" to clock "if0|_if0_p0_leveling_clock_ac_*"
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提问于 2018-08-17 21:06:23 +0800

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