在Riviera-PRO中,Avalon-ST接口VHDL BFM仿真失败

在Aldec®Riviera-PRO™高级验证平台中仿真设计时,Avalon®Streaming(Avalon-ST)接口总线功能模型(BFM)会出现以下错误:

  • Error: "# sim_run" not found in "log.txt". Simulation did not run.
  • Error: Found 3 error(s) in "log.txt":
Error: 1211 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd : (113, 0): Types do not match for port "data_in0". Error: 1212 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd : (113, 0): Types do not match for port "data_out0". Error: 1214 | # SCRIPTER: Error: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/aldec/rivierapro_setup.tcl : (222, 1): Script execution terminated due to error(s).

解决/修复方法

此问题已在Riviera-PRO版本2013.06和13.1Quartus®II软件版本中修复。

要在13.0 Quartus II软件版本中解决此问题,您必须编辑HDL代码,如下所示(斜体修改):

entity altera_avalon_interrupt_sink_vhdl is end altera_avalon_interrupt_sink_vhdl; architecture irq_sink_bfm_vhdl_a of altera_avalon_interrupt_sink_vhdl is -- component altera_avalon_interrupt_sink_vhdl_wrapper -- port ( data_out0 : out integer ); -- end component;

component altera_avalon_interrupt_sink_vhdl_wrapper port ( data_out0 : out std_logic_vector(0 to 31 ) ); end component; signal data_out0 : integer; function aldec_slv2int (val:std_logic_vector) return integer is begin return to_integer(unsigned(val)); end aldec_slv2int;

begin irq_sink_vhdl_wrapper : altera_avalon_interrupt_sink_vhdl_wrapper port map ( aldec_slv2int(data_out0) => data_out0 ); end irq_sink_bfm_vhdl_a;
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提问于 2018-08-06 16:48:25 +0800

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